The present invention relates to a multilevel semiconductor memory device, data writing/reading methods thereto/therefrom, and a storage medium storing data writing/reading programs.
As an error correction function of codes stored in a semiconductor memory device, a method of using Hamming codes has been used. In the semiconductor memory device using the Hamming codes, when four-bit data (m1, m2, m3, m4), for instance is required to be stored, three-check bits (p1, p2, p3) are obtained by a coder, and seven bits in total of the four data bits and the three check bits are stored.
When the Hamming codes stored in the semiconductor memory device are read, the read data (y1, y2, y3, y4, y5, y6, y7) is given to a decoder to obtain error-corrected data (m1, m2, m3, m4). In the above-mentioned semiconductor memory device, it is possible to correct an error of one bit of the read data (y1, y2, y3, y4, y5, y6, y7). For further detail, refer to [Coding Theory] by Hideki IMAI, published by Electronic Information Communications Institute (Ver. 5), Jun. 10, 1994, for instance.
Recently, however, as disclosed by Japanese Laid-Open Patent No. 6(1994)-195987, there has been developed a multilevel semiconductor memory device which can store three or more levels of data each in a single memory cell. A plurality of threshold voltages are set in the multilevel semiconductor memory device. For instance, in the case of four-level non-volatile semiconductor memory, four threshold voltages (0V, 2V, 4V, 6V) are set to each memory cell, respectively, so that two-bit data can be stored in a single memory cell. In other words, the threshold voltage of the memory cell is set to any one of 0V, 2V, 4V and 6V in correspondence to each of four storage contents of (00, 01, 10, 11).
Here, when the error correction function based upon the Hamming codes is provided for the multilevel semiconductor memory device, bits of a code train obtained by the coding are stored in sequence and two adjacent bits are stored in the same memory cell.
For instance, the case where check bits (p11, p21, p31) and (p12, p22, p32) are obtained on the basis of data bits (m11, m21, m31, m41) and ((m12, m22, m32, m42) and further these bits are stored in the multilevel memory cell will be explained hereinbelow. That is, when the Hamming codes composed of these data bits and these check bits are stored in the multilevel memory cell, these bits have been stored in the order of (m11, m21), (m31, m41), (p11, p21), (p31, m12), (m22, m32), (m42, p2), and (p22, p32).
Here, the way of producing an error in the multilevel semiconductor memory devices will be explained hereinbelow by taking the case of the multilevel non-volatile memory. In this case, since an error occurs due to change in threshold voltage, there exists a high possibility that an error occurs in two-bit data at the same time; that is, for example, “10” is changed to “01”.
In other words, the errors caused in the multilevel semiconductor memory device are characterized in that errors occur concentrically in an interval of a code series according to the number of levels to be stored in a single multilevel memory cell. This is referred to as burst error. When this burst error occurs, the storage status of a single multilevel memory cell changes, and thus two-bit error occurs. In this case, since two or more errors occur in a single Hamming code, there exists a problem in that the code cannot be decoded correctly.
As another method, other than the one using the Hamming code, Japanese Patent Laid-Open No. 60(1985)-163300 discloses an error correction method for a multilevel semiconductor memory device that uses multiple codes. In this method, however, the fact that burst errors occur with a high possibility in the case of the multilevel semiconductor memory device is not considered. Thus, there exists a problem in that the error correction efficiency is not high.
Further, in the multilevel memory cell, there exists another problem in that the number of read operations required for a single memory cell increases. Here, a data reading method will be explained hereinbelow by taking the case of the read operation required for the four-level semiconductor memory device. In the semiconductor memory device, when receiving an external read instruction, the memory device waits an input address. In this case, the input address is a logical address not a physical address corresponding to an actual memory cell. The physical address is thus calculated on the basis of the input logical address.
Successively, on the basis of the calculated physical address, it is checked whether the threshold voltage of the designated memory cell is set to any one of 0V, 2V, 4V and 6V. The checked threshold voltage is then converted into two-bit data. In practice, reference voltages (e.g., 1V, 3V and 5V) are applied in sequence to the memory cell. In this case, when the reference voltage of 1V is applied, if a current flows through the source and drain of the memory cell, the threshold voltage of the memory cell is decided as being 0V, so that “00” data can be read. On the other hand, although a current does not flow at 1V, when a current flows at 3V, the threshold voltage of the memory cell is decided as being 2V, so that “01” data can be-read. Further, although the current does not flow at 1V and 3V, when a current flows at 5V, the threshold voltage of the memory cell is decided as being 4V, so that “10” data can be read. Further, when the current does not flow at all the voltages applied to the memory cell, the threshold voltage of the memory cell is decided as 6V, so that “11” is read. In the example, although four levels are set to a single memory cell; that is, two-bit data are stored, the method of writing and reading multilevel data (more than two) has been studied.
In the case of the multilevel memory cell, however, there exists a problem in that the number of read operations required for a single memory cell increases.
For instance, when four levels are stored in a single memory cell as described above, in the four-level semiconductor memory device, three read and check operations must be always executed to specify to which level of the four levels the threshold voltage of the memory cell belongs in each read operation, irrespective of the input address. In practice, although the read and check operations are executed by applying 1V, 3V and 5V stepwise to the memory cell, this is the same as that three read and check operations are necessary.
To overcome this problem, the Inventors have already proposed a method of increasing the read operation speed of the memory cell, in Japanese Patent Laid-Open No. 7(1995)-201189. When this method is explained in correspondence to the four-level semiconductor device, first 3V is applied to the memory cell, and then the high-order bit of the two-bit data is decided according to whether a current flows or not. In this case, when a current flows, the high-order bit is decided as “0”, and when the current does not flow, the high-order bit is decided as “1”. Successively, when the high-order bit is decided as “0”, 1V is further applied to the memory cell. When a current flows, the two-bit data of the memory cell is decided as “00”, and when the current does not flow, the data is decided and output as “01”. On the other hand, when the high-order bit is decided as “1”, 5V is further applied to the memory cell. When a current flows, the two-bit data of the memory cell is decided as “10”, and when the current does not flow, the data is decided and output as “11”. As described above, in this data reading method proposed by the Inventors, it is possible to specify two-bit data stored in a single memory cell by two read operations.
In this data reading method, however, it is always necessary to specify to which level of the four levels the threshold voltage of the memory cell belongs, irrespective of the logical address; that is, even when the logical address designates the high-order bit of the memory cell.
As described above, in the multilevel semiconductor memory device, data are output after the data stored in the memory cell has been perfectly specified in the read operation, irrespective of the input logical address. There exists a problem in that a time longer than necessity is needed, with the result that the data reading speed is inevitably limited.